Analysis of Key Bottlenecks for ChangXin Memory Technologies (CXMT)'s HBM Technology Breakthrough in the Memory Chip Super Cycle

Based on collected industry information and market data, this report provides a detailed analysis of the key bottlenecks that ChangXin Memory Technologies (CXMT) must overcome to achieve HBM technology breakthroughs amid the memory chip super cycle.

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The global memory chip market is currently in an AI demand-driven “super cycle”, which provides an unprecedented development window for domestic memory enterprises. Bernstein defines the current memory market situation as a “super cycle” and predicts that DRAM gross margin may hit a record high of 77% in Q4 2026[1]. By 2026, the total capital expenditure of U.S. tech giants will reach $526.5 billion, a year-on-year increase of 30%, with investments related to AI servers and infrastructure reaching as high as $365.1 billion[1]. AI servers have far higher requirements for memory chip capacity and performance than traditional servers: their DRAM usage is about 8 times that of ordinary servers, and NAND Flash usage is about 3 times[2].

Against this backdrop, HBM (High Bandwidth Memory), as a key component of AI computing, has seen a staggering price increase, with the price of a single HBM3E chip exceeding $400[1]. The HBM market size is expected to grow from $2.9 billion in 2024 to $15.7 billion in 2032, with a compound annual growth rate of 26%[3]. However, the global HBM market is dominated by three giants: SK Hynix, Samsung, and Micron, which together account for over 90% of total production capacity, with orders booked through 2026[4].

As China’s largest integrated DRAM R&D, design, and manufacturing enterprise, CXMT’s Q3 2025 revenue increased 148.80% year-on-year, with comprehensive gross margin rising to 35.00%. Based on Q2 2025 DRAM sales, its global market share has increased to 3.97%[1]. The company has submitted an IPO prospectus to the STAR Market, planning to raise RMB 29.5 billion to build 3 12-inch wafer fabs, with its product portfolio covering mainstream technology platforms such as DDR5 and LPDDR5X[5].

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Through-Silicon Via (TSV) is the core technology for HBM 3D stacking, providing vertical transmission channels for data that can shorten transmission paths by over 90%, and is the foundation of HBM’s high bandwidth and low latency[4]. However, the TSV manufacturing process can be likened to “precision injection for chips”: it requires using lasers or plasma to drill holes with a diameter of 5-10 microns (5-10 times thinner than a human hair) on silicon wafers, followed by a series of processes such as cleaning, coating, copper filling, and polishing[4].

• Aperture Precision Control
  : The TSV aperture must be controlled within the range of 5-10 microns, which requires extremely high precision of etching equipment
• Metal Filling Integrity
  : Copper filling must avoid void formation, otherwise it will lead to reliability failure
• Multi-Layer Stack Alignment
  : When the stack height reaches 16 layers, the micro-bump pitch is less than 10 microns, and any tiny deviation may cause failure[3]

International giants such as SK Hynix have achieved a yield rate of 90% for 16-layer HBM3E, while domestic enterprises are still in the R&D stage for TSV technology[4].

Hybrid bonding technology is the key to achieving ultra-high stacking of 16 layers or more. Compared with traditional micro-bump connections, the copper layer of hybrid bonding is only 1-2 microns thick, with a pitch of 10-15 microns. A single chip can accommodate 100,000 bonding points, with a resistance of only 5 milliohms (1/10 of that of micro-bumps), no transmission gap, and negligible loss[4].

• Precision Alignment
  : The copper layers of two chips must be “precisely aligned” with an error of no more than 1 micron (1/50 the diameter of a human hair), requiring a high-precision alignment system with an accuracy of 0.1 micron[4]
• Low-Temperature Bonding
  : Bonding must be performed below 250℃ to avoid chip deformation, which requires extremely strict process control
• Yield Challenge
  : SK Hynix has achieved a hybrid bonding yield rate of 95%, while domestic manufacturers still face significant challenges in improving yield for this technology[4]

Currently, there are two main technical routes in the market: SK Hynix’s leading MR-MUF, and TC-NCF used by Samsung/Micron. However, for future ultra-high stacking of 16 layers or more, hybrid bonding is regarded as the common evolutionary direction of the industry[6].

Increasing the single Die density of HBM requires adopting more advanced semiconductor manufacturing process nodes, such as migrating from 1z nm to 1b nm, which also falls into the category of front-end processes[6]. At the same time, the Die size of HBM continues to increase (by approximately 15%), leading to a rise in cost per Gb[6].

• In November 2025, CXMT launched DDR5 products with a speed of 80000 Mbps and LPDDR5X products with a speed of 10667 Mbps, whose performance is on par with international first-tier manufacturers[7]. However, in the HBM field, domestic manufacturers are still in the technology accumulation stage
• International giants have already mass-produced 12-layer and 16-layer HBM3E, while CXMT has not yet publicly disclosed its mass production plan for HBM products

EUV lithography machines cannot enter the Chinese market due to U.S. export controls, and the supply of key equipment such as etching machines and thin film deposition equipment is tight[7]. High-end equipment (such as TSV etching machines and hybrid bonding alignment systems) is still subject to external restrictions[4].

The localization rate of core raw materials such as high-end photoresists and ALD precursors is less than 30%, and there is a gap in purity and consistency compared with international advanced levels[7].

Domestic enterprises such as JCET and TFME have built 2.5D/3D packaging production lines that can support HBM3 packaging[4]. However, domestic enterprises are currently focused on HBM3 and lower versions, and their R&D progress for HBM4 is 1-2 years behind that of international giants[4].

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• CXMT’s monthly DRAM production capacity will reach 300,000 wafers by the end of 2025, and its DDR5 market share is expected to jump to 7%[7]
• Focus on yield improvement, with the goal of increasing the yield rate from the current 65% to over 80%[7]

• In the fundraising investment plan, RMB 7.5 billion will be invested in the mass production line technical transformation project, gradually switching processes to mid-to-high-end products, and simultaneously promoting cooperation with local equipment, materials, and component suppliers[5]
• The equipment purchase and installation cost is approximately RMB 4.666 billion, focusing on the introduction of domestic alternative equipment[5]

• It is widely expected in the industry that domestic HBM will be unable to break the monopoly of the international three giants before 2027[7]
• Focus on overcoming core processes such as TSV, hybrid bonding, and 3D stacking
• Goal: Achieve mass production of HBM3/HBM3E products and seize over 20% of the market share[4]

• The total investment of the DRAM technology upgrade project is RMB 18 billion, with equipment purchase and installation accounting for RMB 17.4 billion[5]
• Procurement is planned to start in Q4 2025, with equipment moved in batches from 2026 to 2027[5]

• HBM5 will integrate Near-Memory Computing (NMC) units, allowing memory to handle simple computing tasks[4]
• It is necessary to adapt interfaces with GPU/CPU manufacturers and reconstruct algorithms for AI frameworks

• Pay attention to the supply chain reshaping trend where HBM base die manufacturing shifts from memory manufacturers to TSMC[6]
• Strengthen in-depth cooperation with domestic packaging enterprises (JCET, TFME)

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Bottleneck Category	Specific Content	Breakthrough Difficulty	Expected Breakthrough Time
Process Technology	TSV, Hybrid Bonding, 3D Stacking	★★★★★	2027-2030
Equipment Supply	High-End Etching Machines, Thin Film Deposition Equipment, Hybrid Bonding Alignment Systems	★★★★★	2026-2028
Material Localization	High-End Photoresists, ALD Precursors, Bonding Materials	★★★★☆	2027-2030
Yield Improvement	Increase from 65% to over 85%	★★★★☆	2026-2028
Ecosystem Collaboration	GPU/CPU Interface Adaptation, AI Framework Optimization	★★★☆☆	2028-2030

1. Focus on capacity expansion of mature processes
   , make full use of the price dividends brought by the current super cycle, and accumulate R&D funds
2. Accelerate the introduction of domestic alternative equipment
   , and conduct in-depth cooperation with domestic equipment manufacturers such as NAURA and AMEC
3. Establish a dedicated R&D line for TSV/hybrid bonding
   , recruit overseas talents with high salaries, and quickly narrow the technological gap

1. Equipment Enterprises
   (NAURA, Topping, CSFT): Focus on breaking through TSV etching and thin film deposition equipment
2. Material Enterprises
   (Shanghai Sinyang, Hua Hong Semiconductor): Accelerate the localization of high-end photoresists and electronic specialty gases
3. Packaging Enterprises
   (JCET, TFME): Strengthen the construction of 2.5D/3D packaging capabilities and undertake HBM packaging demands

• Short-term: Focus on the valuation improvement opportunities for equipment and material enterprises brought by CXMT’s IPO
• Mid-term: Focus on performance realization brought by the capacity ramp-up of DDR5/LPDDR5X
• Long-term: Focus on valuation reshaping brought by HBM technology breakthroughs

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The memory chip super cycle provides a valuable development window for CXMT, but also puts forward higher requirements for HBM technology breakthroughs. The core bottlenecks currently faced by CXMT can be summarized as:

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According to general industry expectations, domestic HBM may not break the monopoly pattern of the international three giants until around 2027. If CXMT can seize the super cycle opportunity from 2025 to 2027, complete the capacity ramp-up and yield improvement of DDR5/LPDDR5X, and accelerate R&D on core HBM processes, it is expected to achieve mass production breakthroughs in HBM products by 2030 and enter the first echelon of global memory chip manufacturers.

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[1] Eastmoney - “AI Bubble or Super Cycle? The Price of a Box of Server Memory Can Match the Down Payment for a Small Apartment in Shanghai” (https://caifuhao.eastmoney.com/news/20260111110148239663790)

[2] Jin10 Data - “Is the Memory Super Bull Market Fully Here? Prices Will Continue to Rise in 2026” (https://xnews.jin10.com/details/206394)

[3] Wenxuecity - “The Logic Behind MU’s Skyrocketing Stock Price” (https://www.wenxuecity.com/blog/202512/72453/18439.html)

[4] 36Kr - “10,000-Word Analysis of the 371-Page HBM Roadmap” (https://m.36kr.com/p/3598968891293959)

[5] Yicai Global - “Memory Chip Price Surge Sweeps the Globe, Domestic Semiconductor Equipment Faces Historic Opportunities” (https://www.yicai.com/news/102989986.html)

[6] Tencent Cloud - “HBM Process Breakthrough: Technical Review and Outlook” (https://cloud.tencent.com/developer/article/2608604)

[7] EET China - “2025 Memory Chip Market Summary and Outlook” (https://www.eet-china.com/mp/a463770.html)