In-Depth Analysis Report on TSMC's CoWoS Process Technology Roadmap

Based on comprehensive information collection and analysis, this in-depth research report on TSMC’s CoWoS process technology roadmap is now presented to you.

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CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D advanced packaging technology launched by TSMC in 2012. Its core value lies in realizing multi-chip heterogeneous integration through a

, vertically integrating logic chips and High-Bandwidth Memory (HBM) within the same package [1]. This technology significantly shortens signal transmission distances between chips, reduces latency, and simultaneously improves bandwidth and energy efficiency ratio, emerging as a key underlying technology supporting high-performance computing in the AI era [2].

As Moore’s Law gradually reaches physical limits in front-end manufacturing, the driving force for semiconductor performance growth has shifted from front-end wafer fabrication to back-end advanced packaging. Against this backdrop, TSMC’s CoWoS technology has evolved from “packaging” to “architecture”, becoming a core solution to break through computing power bottlenecks [1].

As of early 2026, TSMC’s CoWoS production lines are nearly fully booked, with premiums for priority production of “hot orders” hitting an all-time high. Securing packaging capacity has become a

for tech giants in building next-generation AI infrastructure [3]. NVIDIA has locked in nearly 60% of TSMC’s total CoWoS production capacity for 2026 to support its transition to a 12-month intensive release cycle [3].

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TSMC’s CoWoS technology has evolved into three main versions, with core differences in

, each optimized for different application scenarios and cost requirements.

Technical Indicator	Detailed Parameters
Interposer Material	Silicon Interposer + TSV (Through-Silicon Via)
Maximum Package Size	Approx. 2,500 mm² (approx. 3.3x reticle size)
HBM Support Capacity	Up to 8 HBM stacks
Manufacturing Cost	High (uses high-purity silicon material and TSV process)
Technology Maturity	High (mass production achieved)
Typical Applications	NVIDIA H100/H200, AMD MI300

CoWoS-S is the earliest launched version with the highest maturity. The silicon interposer features extremely high wiring density and excellent electrical properties, capable of providing hundreds to thousands of interconnect lines with low data transmission latency and crosstalk, making it the preferred solution for AI chip packaging [2]. However, due to the fragile nature of silicon material, yield rate is difficult to meet standards when scaling up size, and manufacturing costs are extremely high [4].

Technical Indicator	Detailed Parameters
Interposer Material	Redistribution Layer (RDL): Composed of polymer and copper wires
Maximum Package Size	Approx. 2,000 mm²
HBM Support Capacity	Up to 6 HBM stacks
Manufacturing Cost	Low
Technology Maturity	Medium (early production capacity stage)
Typical Applications	Networking equipment, edge AI, custom IPUs

CoWoS-R uses an RDL interposer to replace the silicon interposer, offering high flexibility to support more diverse chip sizes and configurations [2]. Although its wiring density and conductivity are inferior to those of silicon interposers, it is sufficient for mid-range or specialized computing (such as AI accelerators). This technology can effectively reduce manufacturing costs and shorten integration time [4].

Technical Indicator	Detailed Parameters
Interposer Material	Local Silicon Interconnect (LSI) + RDL hybrid architecture
Maximum Package Size	Over 3,000 mm² (Gen2 can reach 5.5x reticle size)
HBM Support Capacity	Up to 12 HBM stacks
Manufacturing Cost	Medium (between S and R)
Technology Maturity	High (mass production achieved)
Typical Applications	NVIDIA Blackwell (GB200/GB300), Rubin series

CoWoS-L is a “massive upgraded version” of CoWoS-S, combining the advantages of both silicon interposers and RDL [2]. Local areas use silicon interposers (LSI) for high-speed chip-to-chip interconnections, while other areas use RDL to provide highly flexible integration capabilities. This technology breaks through the yield bottleneck of large-size silicon interposers while retaining the excellent characteristics of silicon interposers, becoming the of TSMC’s advanced packaging [1].

Chart Description: The above chart shows the evolution of TSMC’s CoWoS technology, including: (1) Time evolution trend of interposer size and HBM integration quantity; (2) Comparison of core parameters of the three CoWoS technologies; (3) Capacity expansion plan; (4) Key technology milestone timeline.

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According to the latest plan from TSMC’s 2025 North America Technology Symposium [5]:

Time Node	Technical Specification	HBM Integration	Target Application
2024	CoWoS-L Gen1 (3.3-4.0x reticle)	8 HBMs	NVIDIA Blackwell (B100/B200)
2025	CoWoS-L Gen2 (4.0-4.5x reticle)	12 HBMs	NVIDIA GB300
2026	CoWoS-L Gen2 (5.5x reticle)	12 HBMs	NVIDIA Rubin
2027	CoWoS-L Gen3 (9.5x reticle)	12+ HBMs	NVIDIA Rubin Ultra

• 2027 Mass Production Target:
  Achieve mass production of interposers with a 9.5x reticle size (approx. 12,015 mm²), capable of efficiently integrating 12 or more HBMs with advanced logic chips [1]
• Customer Launch:
  Rubin Ultra is expected to be the first product to adopt the 9.5x reticle specification [5]
• Integrated Power Supply Solution:
  Introduce integrated power supply technology into CoWoS to improve power supply density for AI applications [5]

TSMC is developing the next-generation

, with core innovation in replacing the circular silicon wafer packaging carrier with a square panel [6]:

Technical Indicator	CoWoS (Traditional)	CoPoS (Next-Generation)
Packaging Carrier	12-inch circular wafer (300mm)	Square panel (310×310mm or larger)
Area Utilization Rate	Approx. 70-75%	Approx. 95%+
Number of Chips per Process	16 units (B200)	60+ units
Cost Potential	High	20-30% reduction

• 2026:
  Construct CoPoS pilot production line [1]
• 2027:
  Focus on process improvements to meet partner requirements [1]
• Late 2028-Early 2029:
  Achieve mass production [1]
• Capacity Layout:
  The AP7 factory in Chiayi, Taiwan will become the production center for CoPoS advanced packaging technology [1]

TSMC has also launched

, which uses post-chip process technology and has computing power that of the CoWoS packaging used in the current Blackwell series [5], with mass production expected in 2027. Cerebras and Tesla Dojo have shown strong interest in this technology.

According to reports, NVIDIA is collaborating with TSMC to develop CoWoP packaging technology [4]:

• Core Technology:
  Eliminate the independent underlying substrate and replace it with high-quality Substrate-like PCB (SLP)
• Seven Major Improvements:
  Improved signal integrity, enhanced power integrity, improved thermal performance, reduced PCB thermal expansion coefficient, improved electromigration, reduced ASIC costs, support for more flexible chip module integration methods
• Testing Timeline:
  Functional testing of NVIDIA’s GB100 super chip is expected to be conducted in August 2025 [1]

Chart Description: The above chart shows the timeline of CoWoS technology evolution and the applicability matching of different technology versions in various application scenarios.

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According to industry analysis data [1]:

Time Node	Total Monthly CoWoS Capacity	Monthly CoWoS-L Capacity	Monthly CoWoS-S Capacity	Monthly CoWoS-R Capacity
Q4 2024	35,000 units	10,000-15,000 units	20,000 units	Limited
Q4 2025	75,000-80,000 units	45,000 units	20,000 units	10,000 units
Q4 2026	95,000 units	60,000 units	15,000 units	20,000 units
Q4 2027	135,000 units	85,000 units	10,000 units	20,000 units
2028	150,000 units	120,000 units	10,000 units	20,000 units

• Compound Annual Growth Rate (CAGR) 2022-2026:
  Expected to exceed 50% [4]
• 2024-2025 Target:
  Capacity growth exceeding 100% [4]
• 2025-2026 Target:
  Achieve supply-demand balance [4]
• CoWoS-L Dominance:
  CoWoS-L is expected to account for the main share of future CoWoS series capacity [1]

TSMC is accelerating the global layout of advanced packaging capacity [1]:

Factory/Facility	Location	Expected Timeline	Focused Technology
Zhunan AP6B Plant	Taiwan	Monthly capacity reaches 33,000 units in Q3 2024	Fully automated 3DFabric factory
Taichung AP5B Plant	Taiwan	Operational in H1 2025	Mainly CoWoS, with partial SoIC capacity
Chiayi Science Park Packaging Plant	Taiwan	Completed and equipped in Q3 2025	CoWoS, mass production in 2028
Innolink Nanke AP8 Plant	Taiwan	Pilot production in H2 2025	CoWoS
Kaohsiung K28 Plant	Taiwan	Completed in 2026	CoWoS capacity
Arizona Plant, USA	USA	In planning	CoPoS advanced packaging

• Sustained increase in demand for high-bandwidth packaging for AI training and inference chips [1]
• Major customers such as NVIDIA and AMD continue to launch next-generation AI chips [2]
• Growing demand for self-developed AI chips by major tech companies (e.g., Google TPU, AWS Trainium) [3]

• CoWoS process involves stacking and connecting high-value components such as HBM, making yield control a core challenge [1]
• Long construction cycle and large equipment investment for advanced packaging capacity [3]
• Limited talent and supply chain resources [5]

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As package size and density increase, thermal management and package mechanical stability have become design bottlenecks [2]:

• Multiple reticle stitching is used to manufacture larger-size silicon interposers, but yield control becomes more difficult [1]
• Large-size silicon interposers lead to yield reduction issues [1]
• Hybrid bonding has extremely high requirements for cleanroom environments, comparable to front-end wafer manufacturing [3]

• R&D and factory construction costs for each new process generation grow exponentially [2]
• Long payback period for advanced packaging equipment investment [3]
• Although CoWoS-L has lower costs than CoWoS-S, it is still more expensive than traditional packaging [4]

• Integration of the 6th-generation HBM4 increases technical complexity, requiring extremely high vertical and horizontal interconnect density [3]
• Highly sensitive to thermal deformation during the bonding process [3]
• Packaging is no longer a traditional back-end process, but an integral part of the computing engine [3]

Challenge Type	Solution
Large-size Interposer Yield	Switch to CoWoS-L, adopting LSI+RDL hybrid architecture [1]
Cost Optimization	Develop CoWoS-R for mid-range applications [4]
Panel-Level Expansion	Develop CoPoS technology to improve area utilization [6]
Thermal Management Issues	Explore silicon carbide interposer alternatives [4]

CoWoS has formed two main collaboration frameworks [1]:

1. “TSMC + Third-Party OSAT” Model:
   TSMC completes interposer and stack interconnection (CoW), while packaging (on Substrate) is completed by OSATs such as ASE Group
2. “Third-Party Wafer Fab + OSAT” Model:
   UMC and GlobalFoundries provide interposers, while packaging is completed by ASE Group, Amkor, etc.

• Introduce advanced reticle stitching technology [2]
• Develop new processes for large-size wafer handling [2]
• Explore panel-level packaging to improve yield [5]
• Strengthen full-process quality control system [1]

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Customer	Product Series	Adopted Technology	Mass Production Time
NVIDIA	Hopper (H100/H200)	CoWoS-S	2023-2024
NVIDIA	Blackwell (B100/B200)	CoWoS-L Gen1	Q4 2024
NVIDIA	GB200	CoWoS-L Gen1	2025
NVIDIA	Rubin	CoWoS-L Gen2	2026
NVIDIA	Rubin Ultra	CoWoS-L Gen3	2027
AMD	MI300 Series	CoWoS-S	2024
AMD	MI5XX	CoWoS-L Gen3 + A16	2027
Google	TPU	CoWoS-S/R	Ongoing
Amazon	Trainium/Inferentia	CoWoS-S/R	Ongoing

From Hopper to Blackwell to Rubin, NVIDIA GPU performance has continued to improve significantly [1]:

Generation	Process Technology	Packaging Technology	Core Improvements
Hopper (H100)	4nm	CoWoS-S	Introduced Transformer Engine
Blackwell (B200)	4nm	CoWoS-L	Dual-GPU architecture, 8 HBM3e
Rubin	3nm	CoWoS-L Gen2	12 HBM4, new architecture
Rubin Ultra	3nm/2nm	CoWoS-L Gen3	9.5x reticle, 12+ HBM4e

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Currently, only a few manufacturers such as TSMC, Samsung, and Intel possess

covering advanced logic chip manufacturing, interposer processing, and packaging integration [1].

Manufacturer	Technical Capability	Market Position
TSMC	Full range of CoWoS-S/R/L, SoIC, CoPoS under development	Dominant position (main supplier of AI chips)
Samsung	CoWoS-like solutions	Catching up
Intel	Advanced packaging such as Foveros, EMIB	Actively deploying
ASE Group (OSAT)	Advanced packaging back-end processes	Key partner

• Shift in Equipment Investment Focus:
  From front-end manufacturing to advanced packaging [6]
• Increased Value of Packaging and Testing:
  The value of advanced packaging shifts from 70% in front-end to back-end [1]
• Supply Chain Restructuring:
  Industrial collaboration model shifts from vertical integration to precise collaboration [1]

• Continuous Breakthroughs in AI Computing Power:
  Supports training of trillion-parameter AI models such as GPT-5 [2]
• Improved Energy Efficiency in Data Centers:
  Advanced packaging reduces power consumption and latency [3]
• Expected Cost Reduction:
  Technologies such as CoPoS are expected to reduce unit computing power costs [6]

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1. Continuous Expansion of Package Size:
   Evolve from 3.3x to 9.5x and even larger sizes
2. Increased HBM Integration:
   Develop from 8 stacks to 12 stacks and more
3. Introduction of New Materials:
   Exploration of new materials such as silicon carbide interposers and glass substrates
4. Deepened Heterogeneous Integration:
   Multi-functional integration such as photonic integration and power supply integration

Time Node	Expected Milestones
2025	CoWoS-L becomes the mainstream technology, and supply-demand balance for capacity is achieved
2026	CoPoS pilot production, 5.5x reticle mass production
2027	9.5x reticle mass production, SoW-X begins production
2028	CoPoS mass production, panel-level packaging becomes a new battlefield
2030	8-10x reticle target achieved